Heterogeneous 3D System-in-Package Integration
Advances in 3D integration and packaging technologies now make it possible to build complex systems in single package comprised on multi-technology chiplets.
Historically, advanced integration used monolithic implementations due to power, performance, and cost considerations. With innovations in packaging and stacking technologies, designers can integrate their systems in a single package with chiplets that optimize specific functions using the process technology of choice.
Emerging system requirements demand very high interconnect bandwidth with minimal interface power/bit. Intel provides the two key elements to make this possible—ultra-short-reach interface standard and 3D integration packaging technology.
Intel's Advanced Interface Bus (AIB) is a die-to-die PHY level standard that enables a modular approach to system design with a library of chiplet intellectual property (IP) blocks.
AIB uses a clock forwarded parallel data transfer mechanism similar to DDR DRAM interfaces. AIB is process and packaging technology agnostic—Intel's Embedded Multi-Die Interconnect Bridge (EMIB) or TSMC's CoWoS* for example.
Intel now provides the AIB interface license royalty-free to enable a broad ecosystem of chiplets, design methodologies or service providers, foundries, packaging, and system vendors.
Figure: Example of a possible heterogeneous system in package (SiP) that combines sensors, proprietary ASIC, FPGA, CPU, Memory, and I/O using AIB as the chiplet interface.
Multi-Die Integration with EMIB
- Higher Performance / Bandwidth
SiP integration with AIB and EMIB, enable the highest interconnect density between chiplets. This results in high bandwidth connectivity between the SiP components. In addition, user signals communicating to the external world use standard FCBGA traces, thereby improving signal and power integrity.
- Low Power
Companion chiplets are placed close to each other so the interconnect traces are very short. This enables a low power/bit.
- Small Form Factor
The ability to heterogeneously integrate components in a single package results in small form factors. This helps customers save valuable board space, reduce board layers, and decrease the bill of material (BOM) cost.
- Greater Flexibility, Scalability, and Ease of Use
SiP reduces routing complexity at the PCB level because the components are already in the package. In addition, SiP enhances the ability to incorporate different die geometries in silicon technologies. The net result is a highly flexible, scalable solution that is easy to use.
- Faster Time to Market
SiP enables faster time to market by being able to integrate already proven technology and reuse common devices or tiles across product variants. This saves valuable time and resources, thereby helping customers accelerate their time to market.
Learn More About Heterogeneous 3D SiP Integration
Download this white paper to learn more about how Intel® Stratix® 10 FPGAs and SoCs leverage heterogeneous 3D SiP integration to deliver performance, power, and form factor breakthroughs while providing greater scalability and flexibility. In addition, learn how Intel Embedded Multi-die Interconnect Bridge (EMIB) technology delivers a superior solution for multi-die integration.