FPGA Agilex™ 5 และ FPGA SoC

{"limitDisplayedContent":"showAll","collectionRelationTags":{"relations":{"OR":["etm-ccc32d63096244a298c3da4e9cbc1e44","etm-C25A8CA5-CD4F-4D93-BEB9-57BD5244C3B4","etm-B2A95379-3E9F-4D15-B4B3-8B038858EF8F","etm-48e26217d2b14ecc9878829ce8db151e"],"EXCLUDE":["etm-f6e0d09943a943d383e81b5f64a3956c","etm-ececc448f2f54f0e87cdf5558856b275"],"Child":["743772","772362","735782","762895","744050","762192"]},"featuredIds":["743772","772362","735782","762895","744050","762192"]},"collectionId":"729227","resultPerPage":0.0,"filters":[{"facetId":"ContentType","type":"ContentType","deprecated":true,"name":"ContentType","position":0},{"facetId":"guidetmE4FA8DD33C724A6694B5B0D12AB4C220","field":"stm_10385_th","type":"hierarchical","basePath":"Primary Content Tagging","displayName":" FPGAs Agilex™ 5 FPGAs และ SoC","deprecated":false,"rootFilter":"guidetmE4FA8DD33C724A6694B5B0D12AB4C220","rootPath":["Primary Content Tagging","Intel® FPGA","อุปกรณ์ที่ตั้งโปรแกรมได้ Intel®","เอฟพีจีเอและเอฟพีจีเอ SoC Intel® Agilex™","Intel Agilex® 5 FPGAs and SoC FPGAs"],"position":1},{"facetId":"lastupdated","type":"lastupdated","deprecated":true,"name":"lastupdated","position":2}],"coveoRequestHardLimit":"1000","accessDetailsPagePath":"/content/www/us/en/secure/design/internal/access-details.html","cardView":false,"sorting":"Featured","defaultImagesPath":"/content/dam/www/public/us/en/images/uatable/default-icons","coveoMaxResults":5000,"coveoSplitSize":0,"fpgaFacetRootPaths":"{\"fpgadevicefamily\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Programmable Devices\"],\"quartusedition\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software\"],\"quartusaddon\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® Quartus Software - Add-ons\"],\"fpgaplatform\":[\"Primary Content Tagging\",\"Intel® FPGAs\",\"Intel® FPGA Platforms\"]}","newWrapperPageEnabled":true,"descendingSortingForNumericalFacetsName":"[\"Intel® Quartus® Prime Pro Edition\",\"Intel® Quartus® Prime Lite Edition\",\"Intel® Quartus® Prime Standard Edition\",\"Quartus® II Subscription Edition\",\"Quartus® II Web Edition\"]","columnsConfiguration":{"idColumn":false,"dateColumn":false,"versionColumn":false,"contentTypeColumn":false,"columnsMaxSize":0},"dynamicColumnsConfiguration":[{"name":"DynamicColumn_id","type":"id","gtv":"ID","width":60,"selected":true},{"name":"DynamicColumn_date","type":"date","gtv":"วันที่","width":60,"selected":true},{"name":"DynamicColumn_version","type":"version","gtv":"เวอร์ชั่น","width":135,"selected":true}],"curatedFilter":[{"title":"Recommended Documents","tags":[{"relationship":"AND","value":"Recommended","id":"etm-a065764d12404422a4010b8396828f63"}]},{"title":"Development Software","tags":[{"relationship":"AND","value":"Development Software","id":"etm-ebfe0f9272ba4af9989d1a08f7494bf0"}]},{"title":"Intellectual Property","tags":[{"relationship":"AND","value":"Intellectual Property","id":"etm-0b7580c08e2b4e9eacf848bf52b528e6"}]},{"title":"Datasheet Group","tags":[{"relationship":"OR","value":"Device Overviews","id":"etm-20ef38132a9243a0826bd1e320b198f9"},{"relationship":"OR","value":"Datasheets","id":"etm-d3b801521ba841da80fdd1a3aae06299"},{"relationship":"OR","value":"Errata","id":"etm-73cf3cc1679b467c94e69dbcdde7fc7f"},{"relationship":"AND","value":"Intel® FPGAs PPCH_L1_98836","id":"etm-DA5A91DF-5E20-493F-9B3E-14E037831DF1"}]},{"title":"PCB Resources","tags":[{"relationship":"AND","value":"Intel® FPGAs PPCH_L1_98836","id":"etm-DA5A91DF-5E20-493F-9B3E-14E037831DF1"},{"relationship":"OR","value":"Pinouts and Ballouts","id":"etm-1e82c0064b9249578dabd58249f24c5b"},{"relationship":"OR","value":"Schematic Symbols","id":"etm-33233529087e4a30ae53bd237c7ff622"},{"relationship":"OR","value":"Package Mechanical Drawings","id":"etm-74d5e25294dc439f9f20453c5efa34d6"},{"relationship":"OR","value":"Package Ball Coordinates","id":"etm-6ce1d09c702144759fceb5643cf21399"},{"relationship":"OR","value":"PCB Footprints","id":"etm-cc884f3248024ec5bea738523897de1f"},{"relationship":"OR","value":"Pin Connection Guidelines (PCG)","id":"etm-918f05f708794551a10e44d5545c4d19"},{"relationship":"OR","value":"Net Length Reports","id":"etm-896657cbca054cd2a4ad7d491c1ea1b5"},{"relationship":"OR","value":"Schematic Review Worksheets","id":"etm-8f6fc0d61b3d4e57810103d6dc6bab78"},{"relationship":"OR","value":"Thermal Models","id":"etm-6ea8083418e9459f97d45caa1706bdc3"},{"relationship":"OR","value":"Manufacturing Advantage Services (MAS)","id":"etm-bed5e223670445d9975e40eeca88e3e8"},{"relationship":"OR","value":"PCB Layout and Packaging","id":"etm-25fe5eff5964453ea8870d45d592d4aa"}]}],"updateCollateralMetadataEnabled":true,"relatedAssetsEnable":true,"disableExpandCollapseAll":false,"enableRelatedAssetsOnExpandAll":false,"disableBlueBanner":false,"isICS":false,"isUPE":false}