Intel® Agilex™ FPGA and SoC
Intel® Agilex™ FPGA family leverages heterogeneous 3D system-in-package (SiP) technology to integrate Intel's first FPGA fabric built on 10nm process technology and 2nd Gen Intel® Hyperflex™ FPGA Architecture to deliver up to 40% higher performance1 or up to 40% lower power1 for applications in Data Center, Networking, and Edge compute. Intel® Agilex™ SoC FPGAs also integrate the quad-core Arm* Cortex-A53 processor to provide high system integration.
Intel® Agilex™ FPGA and SoC
Intel® Agilex™ M-Series SoC FPGAs
Optimized for compute and memory intensive applications. With Coherent attach to Intel® Xeon® processors, HBM integration, hardened DDR5 controller, and Intel® Optane™ DC persistent memory support the Intel® Agilex™ M-Series SoC FPGAs are optimized for data-intensive applications which need massive memory in addition to high bandwidth. Coming soon.
Features
Compute Express Link
With the Compute Express Link, Intel® Agilex™ FPGA, and SoC family offers the industry’s first Cache and Memory coherent interconnect to Intel® Xeon® processors. This revolutionary FPGA interconnect will provide low latency and performance gains for memory intensive applications with massive data processing needs.
Transceiver Leadership
Intel® Agilex™ FPGA and SoC family delivers accelerated transceiver innovation with data rates up to 112Gbps and support for PCI Express* up to Gen 5. Intel® Agilex™ FPGA and SoC family will allow customers to choose from a comprehensive transceiver portfolio of 28.3Gbps, 58Gbps, and 112Gbps transceiver tiles. Decoupling the transceiver development accelerates product innovation.
DSP Innovation
Intel® Agilex™ FPGA and SoC family offers a configurable DSP engine which features hardened support for single-precision FP32, half-precision FP16, BFLOAT16, and INT8 calculations. Intel® Agilex™ FPGA and SoC family also supports low- precision configurations from INT7 to INT2 for maximum flexibility. Intel® Agilex™ FPGA programmability, coupled with the innovations in the DSP blocks is ideal for evolving AI workloads.
Heterogeneous 3D SiP Technology
With the proven Embedded multi-die Interconnect Bridge (EMIB) technology, Intel® Agilex™ FPGA, and SoC family offers high density die-to-die interconnect for heterogeneous chips and delivers high performance at low cost. A large library of tiles including transceivers, custom IO, custom compute, and Intel® eASIC™ device tiles provide the agility, flexibility, and customization needed for a variety of applications.
Hardened Protocol Support
Intel® Agilex™ FPGA and SoC family delivers optimal power, performance, and logic utilization efficiency by integrating hardened protocols for many popular functions including 100/200/400G Ethernet, PCIe* Gen 4/5 interface, Interlaken, CPRI, JESD204B/C, and many more.
Memory Integration
Intel® Agilex™ FPGA and SoC family features the industry’s first FPGA support for Intel® Optane™ DC persistent memory. In addition to this, HBM integration allows up to 16GB of external memory to be offered in-package affording up to 512 GB/s of peak memory bandwidth. Dedicated DDR5/4 hard memory controllers will support further on-board DRAM memory expansion.
2nd Gen Intel® Hyperflex™ Architecture
Continuous improvements to the acclaimed Intel® Hyperflex™ architecture deliver improved performance compared to Intel® Stratix® 10 device designs. The 2nd Gen Intel® Hyperflex™ architecture will be extended to all densities and variants of Intel® Agilex™ FPGA and SoC family and thus greatly improve the productivity of customers and reduce time-to-market.
Secure Device Manager
A Secure Device Manager will serve as the central command center for the entire FPGA, controlling key operations, such as configuration, device security, single event upset (SEU) responses, and power management. The Secure Device Manager creates an unified, secure management system for the FPGA fabric, hard processor system (HPS) in SoCs, embedded hard IP blocks, and I/O blocks.
Webinars
The Intel® Agilex™ FPGA and SoC Webinar Series accelerate developers to learn and use Intel® Agilex™ device, features and applications. Register today to attend the live webinars and access on-demand content. Registration links to future sessions will be added as they become available. Check back again at a later date for more details.
For questions about webinars, please e-mail agilex_webinars@intel.com or agwebinars@intel.com.
Webinar Title |
North America |
Europe |
China |
Japan |
Description |
|---|---|---|---|---|---|
| The FPGA for Data Centric World Intel® Agilex™ FPGAs and SoC | October 23rd, 2019 9:00 AM to 9:45 AM PT |
October 22nd, 2019 10:00 AM to 10:45 AM CEST |
December 19th, 2019 |
On demand |
Learn how Intel® Agilex™ FPGAs and SoCs are designed to help engineers quickly deliver optimized acceleration for Intel® Xeon™ processor in the data center, tailor transformation in the network, and low-latency, real-time acceleration at the edge. |
| Intel® Hyperflex™ Architecture Overview for Intel® Agilex™ Devices | November 7th, 2019 9:00 AM to 10:00 AM PT |
November 12th, 2019 10:00 AM to 11:00 AM CET |
January 9th, 2020 10:00 AM to 11 AM CST |
On demand | Learn how the 2nd generation Intel® Hyperflex™ Architecture enables up to 40% higher core performance1, or how the intel process helps reduce power by up to 40% lower power1 in Intel® Agilex™ devices when compared to Intel’s previous generation high-performance FPGAs. |
| Introduction to Intel® Agilex™ FPGA PCI Express* Features |
December 3rd, 2019 9:00 AM to 10:00 AM PT |
December 17th, 2019 10:00 AM to 11 AM CET |
January 16th, 2020 10:00 AM to 11:00 AM CST |
On demand | Learn how Intel® Agilex™ PCIe* Gen4 solution delivers 2X more PCIe* bandwidth2 compared to previous generation of Intel FPGAs, enabling coherent connection and faster connectivity to future select Intel® Xeon® Scalable processors. |
| Introduction to Intel® Agilex™ FPGAs External Memory Interfaces |
January 16th, 2020 9:00 AM to 10:00 AM PT |
January 21st, 2020 10:00 AM to 11:00 AM CET |
February 20th, 2020 10:00 AM to 11:00 AM CST |
On demand |
Learn how Intel® Agilex™ FPGAs and SoCs provide DDR4 interface running at up to 3.2 Gbps and how to take advantage of resource sharing to implement multiple interfaces in a single device. |
| Intel® Agilex™ Ethernet Support: E-Tile Transceiver Basics |
On demand |
On demand |
On demand |
Learn how to build a high-speed interface using E-tiles, whether your target application requires Ethernet, FibreChannel, Common Public Radio Interface (CPRI) or even your own proprietary, non-standard protocol. |
|
| Intel® Agilex™ Ethernet Support: Configuring the E-Tile Hard IP for Ethernet |
On demand |
On demand |
On demand |
On demand |
Learn how to customize the Hard IP for Ethernet block found in Intel® Agilex™ F-Series’ E-Tiles. |
| Intel® Agilex™ Ethernet Support: E-Tile Clocking |
On demand |
On demand |
On demand |
On demand |
Learn the various clocking resources found in Intel® Agilex™ F-Series as well as their usages and connectivity. |
| Intel® Agilex™ SoC FPGA Hard Processor System (HPS) Overview |
On demand |
On demand |
On demand |
On demand |
Learn about the architecture of the Intel® Agilex™ 10 SoC FPGA, and the Hard Processor System (HPS) as well as its contents. |
| Intel® Agilex™ Board Design Considerations |
Coming soon |
Coming soon |
Coming soon |
Coming soon |
Coming soon |
Introduction to First Shipping Intel® Agilex™ FPGA
Watch this video introducing the power-on and initial operational results of the first FPGA for the data-centric world.
Intel® Agilex™ Device PCIe* Gen4 x16 Demo
Watch this demo of PCIe* Gen4 x16 operation in the first Intel® Agilex™ device.
Intel® Agilex™ Device DDR4 Demo
Watch this demo video of the Intel® Agilex™ device with DDR4 in action.
Intel® Agilex™ Device 100G Ethernet Demo
Watch a demonstration of first Intel® Agilex™ device delivering 100G Ethernet capability.
Intel® Agilex™ SoC FPGA Hard Processor System (HPS) Demo
See the Hard Processor System (HPS) in the first Intel® Agilex™ SoC boot up with Linux.
Intel® Agilex™ FPGA 58G XCVR Transceiver Demo
See the transceiver performance of the first Intel® Agilex™ FPGA delivering 58G data rates.
Intel® Agilex™ FPGA and SoC Family
Watch this video to learn more about how Intel® Agilex™ FPGA and SoC family delivers customized connectivity, low latency, maximum data throughput, and customized acceleration by combining agility and flexibility to process, store, and move data for data-centric applications.
Intel® Agilex™ FPGA and SoC Architecture
Significant architectural improvements, DSP innovations, and fundamental changes in routing and layout combine to deliver up to 40% higher performance1 or 40% lower power1 with the Intel® Agilex™ FPGA and SoC family. Checkout the video to learn more!
112G PAM-4 Transceivers
Intel® Agilex™ FPGA and SoC family offers new levels of performance using Intel’s Advanced 10nm FinFET Process. 112Gbps serial transceiver links support demanding bandwidth requirements in next-generation data center, enterprise, and networking environments.
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