Digital Signal Processing
Variable-precision DSP architecture with hardened floating-point operators integrated into Generation 10 FPGAs and SoCs.
Intel offers exclusive hard floating-point solutions. The revolutionized hardened DSP blocks are industry’s first with native support for IEEE 754 single-precision floating point in dedicated hardened circuitry. This technological breakthrough allows the variable-precision DSP blocks to be configured at compile time into the IEEE 754 floating-point, standard-precision (18 bit), or high-precision (27 bit) mode.
In floating-point mode, each DSP block provides a single-precision multiplier and single-precision adder enabling DSP designers with the following key benefits:
- Shortened development time: Using FPGAs with native floating-point operators eliminates the need to convert your floating-point designs to fixed-point designs, overcoming an already challenging and lengthy task. The productivity advantages of not having to convert to fixed-point design are further amplified as you iterate your design.
- Improved floating-point performance: Past floating-point implementations were limited in performance due to timing bottlenecks by additional logic and routing resources required to implement floating-point operators. With native support for floating point in the new variable-precision digital signal processing (DSP) blocks, floating-point operations can run at the frequency of the DSP blocks, delivering significantly higher performance.
- Higher resource efficiency: Past floating-point implementations required additional logic and routing resources, large complex floating-point designs would run out of logic before DSP blocks. DSP blocks with hardened floating point allow designers to fully utilize all floating-point operators in all of the DSP blocks while lowering power and enabling more logic to be available for additional features and functions.
Three DSP block modes available in Intel® Arria® 10 and Intel® Stratix® 10 FPGAs and SoCs
- Floating-point mode (Hardened IEEE 754 operators)
- Standard-precision mode (18-bit fixed-point multipliers)
- High-precision mode (27-bit fixed-point multipliers)
DSP Builder for Intel® FPGAs
DSP Builder for Intel® FPGAs is a digital signal processing (DSP) design tool that allows push button Hardware Description Language (HDL) generation of DSP algorithms directly from MathWorks Simulink* environment. DSP Builder for Intel® FPGAs adds additional Intel libraries alongside existing Simulink* libraries with the Intel® DSP Builder Advanced Blockset and DSP Builder Standard Blockset. Check out the latest tool capabilities and detailed features by visiting the DSP Builder for Intel® FPGAs page.
Intel’s intellectual property (IP) portfolio includes a unique combination of DSP IP cores and Forward Error Detection and Correction IP cores that complement DSP Builder for Intel® FPGAs Advanced Blockset Design Examples. Find the right DSP IP for your designs here.
Includes documentation regarding devices, IP cores, white papers, and reference designs.