FPGA Military, Aerospace, and Government Design
Direct RF Design Examples
View featured videos or read solution briefs.
ADC/DAC Cockpit Design Example Video
Wideband Channelizer Design Example Video
Time-Delay Beamformer Design Example Video
Solution Briefs |
Description |
Features |
Applications |
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To help new users comprehend Intel® Stratix® 10 AX FPGA capabilities quicker and allow out-of-the-box evaluation capability, Intel developed an analog-to-digital converter (ADC) or digital-to-analog converter (DAC) cockpit design example. This design features a graphical user interface (GUI) to explore and configure the analog tile blocks with a variety of settings. These include configuring the decimation or interpolation modes of up/down converters, center frequency of course and fine tuners, setting loopback modes, sample rate, and so on. |
Sampling rate up to 64 GSPS NCO Configuration Decimation/Interpolation Modes Settings ADC Waveforms viewer DAC Waveform Generator Multi-Port Synchronization RF Performance Characterization Intel Stratix 10 AX FPGA Development Kit |
ADC/DAC Evaluation |
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| To showcase Intel Stratix 10 AX FPGA capabilities, Intel developed a Wideband Channelizer design example. This design features a polyphase filter bank developed using a DSP Builder for Intel® FPGAs' design tool oriented for DSP developers. Data from the analog-to-digital converter (ADC) is streamed into the channelizer block that includes prototype polyphase filter and 64 phases FFT block. | Sampling rate 51.2/64 GSPS Dynamic spectral viewer Spectrogram viewer DSP Builder for Intel FPGA Intel Stratix 10 AX FPGA Development Kit |
Electronic countermeasures Test and measurement equipment Communication systems |
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| Time-Delay Beamformer | Digital Time Delay Beamforming offers arbitrary angular resolution, simultaneous beams at different angles, and makes no compromise in quality. This design features a super sample rate fractional delay resampler filter in the time delay engine developed using a DSP Builder for Intel® FPGAs' design tool oriented for DSP developers. There are four instances of the time delay engine to support four simultaneous beams, where each beam is independent and controlled separately. |
Sampling rate 51.2GSPS 8 RX Elements Array 4 beams with 1.6GHz Bandwidth Fractional delay filter RX Phased Array Synchronization DSP Builder for Intel FPGA Intel Stratix 10 AX FPGA Development Kit |
Active electronically scanned array (AESA) Radar and Sonar Wideband Communication Radio Astronomy |
| Multiple Device Synchronization | To showcase Intel Stratix 10 AX FPGA synchronization capability, Intel developed a multiple device synchronization design example. This design demonstrates the deterministic latency link between two analog-to-digital converter (ADC) or digital-to-analog converter (DAC) nodes by JESD204C subclass1 protocol, latency alignment, and phase alignment between different ports in local and remote devices. | Sampling rate 48GSPS RX and TX Phased Array Synchronization Deterministic FPGA Interconnection Intel Stratix 10 AX FPGA Development Kit |
Active electronically scanned array (AESA) Radar and Sonar Electronic Countermeasures |
Featured Content
Application Design Examples
The following design examples contain highly parameterized designs with simulation or in-hardware implementation working with an Intel® FPGA development board. For more information, Contact Intel.
Data Sheet |
Description |
Features |
Applications |
Publish Date |
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This design features a polyphase filter bank developed using a DSP Builder for Intel® FPGA design tool oriented for DSP developers. Data from On-chip Signal Generator is streamed into Channelizer block that includes Commutator, Polyphase Filters, Circular Shifter, and FFT block. Captured output of the Channelizer is uploaded to host and presented in viewers, while showing some key signal quality metrics. Oversampled Channelizer design includes an On-chip Signal Generator, which can provide programmable stimulus to Channelizer system, making the design example run without external signal generator and ADC. |
Sampling Rate Support: 24GSPS Support 256 Channels Polyphase signal processing infrastructure Dynamic Spectrum/Spectrogram View Time domain waveform View RF Performance measurements On-chip Signal Generator Intel® Agilex™ FPGA Development Kit |
Radar and Electronic Countermeasures Test and Measurement equipment Communication Systems |
June 2022 |
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| MVDR adaptive beamformer example design shows efficient implementation of adaptive beamforming on Intel® FPGAs. Adaptive beamformer achieves optimal signal quality from desired direction, while suppressing the interferences from undesired direction. MVDR is based on Sample-Matrix-Inversion method, where the beamforming weights are calculated based on direct observation of the environment. | MVDR algorithm Linear-phased array Array size 8 and 64 Multi-beam adaptation Intel Code Builder for OpenCL™ application programming interface (API) Intel® Arria® 10 FPGA Development Kit |
Radar Sonar Electronic countermeasures Communication systems Microphone arrays |
July 2019 |
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Channelizer is a wideband receiver that splits a wide bandwidth into individual bands of interest. As a result of processing gain, low signal-to-noise ratio (SNR) signals can be reliably detected in individual subchannels. |
Programmable super sample rate fast Fourier transform (FFT) IP Programmable Poly-Phase Filter-Bank IP FFT Optimized for Real Input Samples JESD204B interface to Analog Devices* 3GSPS 14 bit dual channel analog-to-digital converter (ADC) AD9208 Intel® Stratix® 10 FPGA |
Wideband communication systems Cable system Measurement equipment |
September 2018 |
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Intel Radar waveform classification example design is built to recognize unique micro-Doppler signatures of different targets using a convolution neural network (CNN) model. |
Micro-Doppler classification Real-time radar waveform recognition Intel Distribution of OpenVINO™ toolkit Intel® Arria® 10 FPGA Development Kit board |
Autonomous vehicles Surveillance radar for military Robotics |
June 2018 |
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| Image Formation in Synthetic-Aperture Radar (SAR) | Synthetic Aperture Radar (SAR) is a technique used in modern radars to acquire high-resolution images of scene. Intel® FPGAs are enabling such technology even under tight SWaP constrains. | Global back-projection image formation Efficient and scalable array architecture Floating point on FPGA Intel® Stratix® 10 FPGA |
Synthetic Aperture Radar (SAR) Synthetic Aperture Sonar (SAS) |
April 2018 |
Semantic Segmentation is used in a variety of self-navigating robotic applications. The application is to classify the type of object that each pixel in the image belongs to. This example shows the detection and segmentation of houses from overhead imagery. |
Mini U-Net-based semantic segmentation demo Intel® Arria® 10 FPGA Development Kit SpaceNet Dataset Intel Distribution of OpenVINO toolkit |
Deep learning Navigation Optical surveillance Satellite imaging |
April 2018 |
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Monobit Digital RF Memory design example demonstrates the usage of Intel® FPGA integrated high-speed transceivers as a wideband front-end stage. |
Monobit Receiver/transmitter 12.5 GHz instantaneous bandwidth Digital dithering Digital channelizer Intel® Stratix® 10 FPGA |
Electronic countermeasures Signal intelligence (COMINT/ELINT) Communication systems |
March 2017 |
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The Partition-Based Security design example demonstrates a secure way of assignment of security keys to multiple encrypted partial regions in the Intel® FPGA. |
Secure partial reconfiguration (PR) Simultaneous support for both one-time programmable (OTP) key and battery-backed key Qcrypt security tool PR configuration from EPCQ flash Intel® Arria® 10 FPGA with SoC Development Kit |
Data center/ multi-tenancy Automotive Secured communications commercial off-the-shelf (COTS) boards Applications requiring multi-level security |
March 2017 |
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| Pulse Doppler | This design example demonstrates Pulse Doppler processing. In typical radar application there is a requirement to calculate and identify Doppler frequencies. This is done by calculating FFT across multiple coherent radar pulses. Due to inherent write/read pattern of dynamic memories, the corner turn operation is inefficient. This design shows how to mitigate the throughput bottleneck as a result of corner turn. |
Efficient corner-turn implementation Fixed point and Floating point FFT example for Pulse Doppler |
Electronic countermeasures Radar |
October 2016 |
| This reference design includes the generation of a Wideband Gaussian Noise signal using a poly-phase approach. The subsequent signal processing enables you to populate only desired spectral bands with custom-defined magnitude for each band. | Wideband Gaussian Noise source – 2.5 GHz Digital filter banks Fine spectral resolution < 2.5 MHz Dynamic band and magnitude control Floating-point processing in FPGA Intel® Arria® 10 FPGA AD9162 – 5GSPS digital-to-analog converter (DAC) with JESD204B interface |
Electronic countermeasures Radar Communication systems Hardware accelerated simulations |
June 2016 | |
The FFT beamforming demo generates multiple beams simultaneously for spatial filtering. This translates to better performance, which is an essential requirement for real-time systems. |
Programmable super sample rate FFT IP FFT beamforming targeting linear array FFT beamforming targeting planar array |
Radar Radiology Radio astronomy |
April 2016 |
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The QR Decomposition Solver design example is a parameterizable implementation designed to solve various matrix sizes. QR-based algorithm has good numerical stability and can solve rectangular, over-determined equation systems. The algorithm is one of the first complex floating-point reference designs highlighting feasibility and performance of floating-point IP on FPGA. |
Linear equation system solver Parameterizable and scalable IP Throughput acceleration Power efficiency Floating point |
Radar and sonar STAP algorithm Adaptive beamformer Scientific computing Adaptive filtering |
April 2014 |
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| The Extended Kalman Filter (EKF) is implemented on the Cyclone® V SoC. It efficiently utilizes a hybrid architecture, where a portion of the algorithm is offloaded to the FPGA fabric to increase overall system performance and offload the Arm* processor. | Matrix co-processor IP Doubles CPU system performance† Compact FPGA footprint Cyclone V SoC |
Radar and sonar Guidance and navigation Inertial navigation sensors Sensor fusion Motor control |
February 2014 |
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| Linear Solver with Cholesky Decomposition | The Cholesky Decomposition Solver design example is a parameterizable implementation designed to solve various matrix sizes. Cholesky-based algorithm can solve private case of square equation system, in more efficient way than other algorithms like QR. The algorithm is one of the first complex floating-point design examples highlighting feasibility and performance of floating-point IP on FPGA. |
Linear equation system solver Parameterizable and scalable IP Throughput acceleration Power efficiency Floating point |
Radar and sonar STAP algorithm Adaptive beamformer Scientific computing Adaptive filtering |
February 2014 |
| Oversampling Channelizer with Spatial Overlapping | This is a subset of wideband SSR oversampling channelizer. The implementation architecture of an oversampling channelizer can be very different depending on the input sample rate, number of channels, and number of overlapping samples. In this architecture, the number of FFT channels is low, the number of overlapping samples is less than the number of parallel paths. Overlapping inputs happen across the parallel paths, thus the term 'spatial overlapping'. | Efficient parallel architecture Complex or real input Natural channel order output Operating clock independent of sampling rate |
Electronic countermeasures Radar Communication systems |
February 2014 |
The Time Delay Beamforming design example is implemented in the Stratix V DSP Development Kit. True time delay is achieved through a fractional delay filter with arbitrary fine resolution. The design example covers a simple but complete transmit and receive pulsed radar system with 32 phased array elements. |
Wideband beamforming Arbitrary steering angle Scalable design |
Active electronically scanned array (AESA) Radar, Sonar Phased array radio telescope Electronic countermeasures |
February 2014 |
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| In a typical pulsed radar, Pulse Compression correlates receive signal with a known waveform to increase the range resolution and SNR. This design example demonstrates Pulse Compression with Overlap-and-Save technique. | Pulse radar range resolution increase Increase detection SNR FFT-based fast convolution |
Electronic countermeasures Radar |
December 2013 |
Video Archive
SpaceNet* Semantic Segmentation
Satellite imagery segmentation to classify the type of object that each pixel in the image belongs to. This example shows the detection and segmentation of houses from overhead imagery implemented on Intel® FPGA.
Model Based Design
DSP Builder for Intel® FPGA is a model based tool to synthesize DSP processing blocks and IP into FPGA. This video shows the typical DSP design flow and how DSP Builder based flow provides great productivity enhancement for system designers.
Radar Waveform Classification
One of the common tasks in defense applications is to extract parameters and classify waveforms. In this video we will show how Intel® FPGA was used to perform object classification in radar using micro-Doppler signal returns.