What's New in Intel® Quartus® Prime Software

Power and Performance

Intel® Agilex™ Device Support

The Intel® Quartus® Prime Pro Edition Software v21.3 supports the Intel® Agilex™ device family. These innovative FPGAs leverage heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10 nm SuperFin Technology and 2nd Generation Intel® Hyperflex™ FPGA Architecture to deliver up to 45% higher performance (geomean vs. Intel® Stratix® 10)1 or up to 40% lower power.1

Compilation Strategies

The compiler in the Intel Quartus Prime Pro Edition Software is a fast, multi-faceted tool, allowing different compilation strategies that meet the designer’s needs. In addition to standard compilation, which can give you a baseline for performance, there are other compilation options available:

  • NEW - Fast compile for small designs can be used to get quick compiles at the beginning of the development process when only a small portion of the design has been implemented.
  • NEW - Fast Functional Test Compilation is used to get a quick check on the functional performance of your RTL. Hold timing optimization is performed with no setup optimization. Used to functionally validate hardware where Fmax is not critical.
  • IMPROVED - Aggressive Compile Time provides a middle ground between the Fast Functional Test Compilation and the default compilation option. Faster compiles with only a moderate decrease of Fmax.
  • High-effort compilation is used to make the compiler maximize its effort to get the best performance results out of a design.
  • IMPROVED - Engineering Change Order (ECO) compilation is used when only minor changes are needed to an otherwise good compile. ECO compiles can provide a compilation speedup of 5X – 10X.2 It replaces the Rapid Recompile flow for post-fit Signal Tap changes with significant compilation speedup.

Additionally, there are many other parameters available to customize your compilation strategies to meet your specific requirements.

Nios® V

Nios V is the next generation softcore processor for Intel® FPGAs, based on the RISC-V instruction set architecture. It leverages the fast-growing open-source ecosystem for RISC-V based processors.

  • The first variant is the Nios V/m
  • Based on the RISC-V:RV32IA classification
  • 32-bit ISA
  • 5-stage pipeline
  • AXI4 interfaces
  • Intel Hardware Abstraction Layer (HAL) and uC/OS-II support
  • More than 5x the performance of the Nios® II/e core

Ease of Use

Design Assistant / Snapshot Viewer

The Design Assistant and Snapshot Viewer are productivity tools meant for novice and advanced users. These tools enable faster design closure by reducing the number of design iterations required and speed every iteration with targeted sanity checks and guidance at every stage of the compilation process. View the video to learn more about the Design Assistant and Snapshot Viewer.

In the Intel® Quartus® Prime Pro Edition Software v21.3, we have continued to add new rules as well as refining many of the existing rules to make it more useful for getting to timing closure faster. Additionally, performance improvements have been made to the static timing analysis engine. Many of the Design Assistant rules support cross probing to timing reports to make it easier to investigate paths.

New Reports

The Intel® Quartus® Prime Pro Edition Software continues to expand its rich set of compilation reports. In the v21.3 software release, the following new reports have been added:

  • Report Clock Networks
  • Report Exceptions Reachability (beta)
  • Report Timing by Source Files

And the static timing analysis report tasks have been reorganized to make it easier to get to the most commonly used tasks.

In addition to the new and improved reports, cross-probing between reports is supported in many of them. This expanding portfolio of reports enables you to gather detailed information about routing, congestion, timing, tension, span, routing effort, and many other metrics that will provide rapid feedback for closing timing quickly.

Debug Tools

Preserve Signals for Debug

Preserving signals for debug in Quartus RTL flow as well as Platform Designer allows the designer to maintain visibility of nodes throughout the compilation.  The marked nodes then show up in the Node Finder GUI when using the Quartus Debug Tools.  Marking signals to preserve for debug can be done on a signal by signal basis, at the instance/entity level, or turned on and off for the entire design through pragmas (Verilog) or Attributes (VHDL). 

A report is provided that will show all the signals that have been preserved and that the desired settings are applied successfully.

Incremental Signal Tap with ECO Compiler

Many new features have been added to the ECO Compiler used for incremental Signal Tap compilations.

  • Change post-fit tap inputs to Basic OR trigger
  • Change advanced trigger (post-fit inputs and/or logic)
  • Increase number of post-fit tap targets
  • Convert pre-synthesis tap to post-fit tap

Additionally, improvements have been made to the Signal Tap GUI to make these features more intuitive to use. The ECO compiler provides a significant improvement in recompile times when using Signal Tap at the final stages of design validation.

Simulator Aware Signal Tap (Beta)

An exciting new innovation, adding simulator aware Signal Tap nodes, is available with the version 21.3 release of the Intel® Quartus® Prime Pro Software Edition. Designers can use the full power of an RTL simulator to extend the reach of their Signal Tap data that was taken from their FPGA design.

Instead of selecting individual nodes, the user selects hierarchies or instances that they want to debug. The new intelligent node finder will identify clock domains and nodes that are required to provide full visibility into the instance. Once Signal Tap data has been captured, the user exports that data into their preferred RTL simulator. Quartus will generate simulation scripts as well as export captured data to be loaded into the simulator as the starting point for the simulation. From there, the user can get full visibility into their design using the Signal Tap data as the initial conditions for the simulation. This alleviates users from having to go through so many iterations of adding or changing Signal Tap nodes and recompiling, saving the designer significant time in the debug and validation stage.

Remote Debug

The remote debug solution has been extended to use the ARM HPS to communicate over Ethernet or PCIe. 

For full details visit Rocketboards.org.

 

Tile Interface Planner

The Intel® Quartus® Prime Tile Interface Planner is a new feature that helps you to quickly place component IP in legal tile locations of F-tile. Tile Interface Planner is an interactive floorplanning tool that simplifies legal placement of component IP on device tiles.

Tile Interface Planner displays your project component IP in a hierarchical tree view, next to a visual representation of the device tile segments. You can then locate the potential legal locations for each IP within the tile, place the IP at the location, and apply the placement constraints to the project for downstream Compiler stages.

Partners

Questa*-Intel® FPGA Edition Software

The Questa*-Intel® FPGA Edition software from Mentor Graphics (A Siemens EDA company) is here! Questa*-Intel® FPGA Edition is the core simulation and debug engine of the Questa Verification Solution providing the latest in FPGA simulation technology. Questa-Intel FPGA Edition has up to 2.5x speedup for Verilog and 1.25x speedup for VHDL over the ModelSim*-Intel® FPGA Edition software. It is a full 64-bit version with support for both Windows 10 and Linux.

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® Prime Design Software.

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