High-Level Synthesis Advanced Optimization Techniques (IHLS2DAYPART2)

Course Description

In the class, you will learn how to use advanced techniques using the Intel® HLS Compiler to create an optimized IP for Intel® FPGAs. We will cover using recommended techniques to improve loop pipelining performance. We will discuss how the Intel HLS compiler generates and optimizes local memory architecture as well as how to best guide the compiler to create never-stall local memories. Lastly, we will use several real-life design examples to demonstrate the optimization flow.

At Course Completion

You will be able to:

• Use the Intel HLS Compiler generated HTML reports to locate performance bottlenecks in a component
• Effectively pipeline loops by removing data and memory dependencies
• Use Pragmas to control HLS loop performance
• Optimize Local Memory Architecture
• Use all the optimization tool available in the Intel HLS Compiler to create a high-performance FPGA IP

Skills Required

• Basic understanding of the C programming language
• Basic usage with the Intel HLS Compiler; specifically attendance of the "Introduction to High-Level Synthesis with Intel FPGAs" course

Prerequisites

We recommend completing the following courses:

• Introduction to High-Level Synthesis with Intel® FPGAs
• The Intel® Quartus® Prime Software Design Series: Timing Analysis with Timing Analyzer
• The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
• The Intel® Quartus® Prime Software: Foundation (Pro Edition) (Online Training)
• Timing Analyzer: Introduction to Timing Analysis

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• SW Developer for C Programming - 300 Level

Class Schedule

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Location	Dates	Price	Registration
Virtual Classroom (9:00am-1:30pm Pacific Time)	02/08/2021 - 02/09/2021	Free	Register Now

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