set_output_delay (::quartus::sdc)

Tcl Package and Version

Syntax

set_output_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name> ] [-rise] [-source_latency_included] <delay> <targets>

Arguments

-h | -help

Short help

-long_help

Long help with examples and possible return values

-add_delay

Create additional delay constraint instead of overriding previous constraints

-clock <name>

Clock name

-clock_fall

Specifies output delay relative to the falling edge of the clock

-fall

Specifies the falling output delay at the port

-max

Applies value as maximum data required time

-min

Applies value as minimum data required time

-reference_pin <name>

Specifies a pin or port in the design to which the output delay is relative

-rise

Specifies the rising output delay at the port

-source_latency_included

Specifies input delay already includes added source latency

<delay>

Time value

<targets>

Collection or list of output ports

Description

Specifies the data required times at the specified output ports
relative the clock specified by the -clock option. The clock must
refer to a clock name in the design.

Output delays can be specified relative to the rising edge (default)
or falling edge (-clock_fall) of the clock.

Output delays can be specified relative to a pin or a port (-reference_pin)
in the clock network. Clock arrival times to the reference pin or port
are added to the data required time.

If no -reference_pin is specified, if the output delay is specified
relative to a generated clock with a single target, the clock arrival
times to the generated clock are added to the data required time. If the
generated clock has multiple targets, the worst case arrival time to
those targets will be used.

Output delays can include clock source latency. By default the clock
source latency of the related clock is added to the output delay
value, but when the -source_latency_included option is specified, the
clock source latency is not added because it was factored into the
output delay value.

The maximum output delay (-max) is used for clock setup checks or
recovery checks and the minimum output delay (-min) is used for clock
hold checks or removal checks. If only one of -min and -max (or
neither) is specified for a given port, the same value is used for
both.

Separate rising (-rise) and falling (-fall) required times at the port
can be specified. If only one of -rise and -fall are specified for a
given port, the same value is used for both.

By default, set_output_delay removes any other output delays to the port
except for those with the same -clock, -clock_fall, and -reference_pin
combination. Multiple output delays relative to different clocks, clock
edges, or reference pins can be specified using the -add_delay option.
Future output delays relative to different clocks, clock edges, or
reference pins that do not specify the -add_delay option will still
remove previous output delays that specified the -add_delay option.

The value of the targets is either a collection or a Tcl list of
wildcards used to create a collection of the appropriate type.
The values used must follow standard Tcl or Timing Analyzer-extension
substitution rules.  See help for the use_timing_analyzer_style_escaping 
command for details.

Example Usage

# Simple output delay with the same value for min/max and rise/fall:
# 1) set on ports with names of the form myout*
set_output_delay -clock clk 0.5 [get_ports myout*]
# 2) set on all output ports
set_output_delay -clock clk 0.5 [all_outputs]

# Output delay with respect to the falling edge of clock
set_output_delay -clock clk -clock_fall 0.5 [get_ports myout*]

# Output delays for different min/max and rise/fall combinations
set_output_delay -clock clk -max -rise 0.5 [get_ports myout*]
set_output_delay -clock clk -max -fall 0.4 [get_ports myout*]
set_output_delay -clock clk -min -rise 0.4 [get_ports myout*]
set_output_delay -clock clk -min -fall 0.3 [get_ports myout*]

# Adding multiple output delays with respect to more than one clock
set_output_delay -clock clkA -min 0.2 [get_ports myout*]
set_output_delay -clock clkA -max 0.8 [get_ports myout*]
set_output_delay -clock clkA -clock_fall 0.6 [get_ports myout*] -add_delay
set_output_delay -clock clkB -min 1.1 [get_ports myout*] -add_delay
set_output_delay -clock clkB -max 1.5 [get_ports myout*] -add_delay

# This is a common mistake where output delays are accidentally removed
set_output_delay -clock clkA -min 0.2 [get_ports myout*]
set_output_delay -clock clkB -min 1.1 [get_ports myout*] -add_delay
# The following removes the clkB entry. You need to always use -add_delay 
#     when more than one clock, clock_fall or reference_pin exists
set_output_delay -clock clkA -max 0.8 [get_ports myout*]
# The following removes the clkA entry. You need to always use -add_delay 
#     when more than one clock, clock_fall or reference_pin exists
set_output_delay -clock clkB -max 1.5 [get_ports myout*]

# Specifying an output delay relative to an external clock output port
set_output_delay -clock clk -reference_pin [get_ports clkout] 0.8 [get_ports myout*]

# Specifying an output delay relative to the clock pin of a register
set_output_delay -clock clk -reference_pin [get_pins regA|clk] 0.8 [get_ports myout*]

Return Value

Code Name

Code

String Return

TCL_OK

0

INFO: Operation successful

TCL_ERROR

1

ERROR: Incorrect collection type. Expected a collection of type <string>.

TCL_ERROR

1

ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist.

Tcl Package and Version	Belongs to ::quartus::sdc 1.5
Syntax	`set_output_delay [-h \| -help] [-long_help]` `[-add_delay]` `-clock` <name> `[-clock_fall]` `[-fall]` `[-max]` `[-min]` `[-reference_pin` <name> `]` `[-rise]` `[-source_latency_included]` <delay> <targets>
Arguments	`-h \| -help`		Short help
	`-long_help`		Long help with examples and possible return values
	`-add_delay`		Create additional delay constraint instead of overriding previous constraints
	`-clock` <name>		Clock name
	`-clock_fall`		Specifies output delay relative to the falling edge of the clock
	`-fall`		Specifies the falling output delay at the port
	`-max`		Applies value as maximum data required time
	`-min`		Applies value as minimum data required time
	`-reference_pin` <name>		Specifies a pin or port in the design to which the output delay is relative
	`-rise`		Specifies the rising output delay at the port
	`-source_latency_included`		Specifies input delay already includes added source latency
	<delay>		Time value
	<targets>		Collection or list of output ports
Description	Specifies the data required times at the specified output ports relative the clock specified by the -clock option. The clock must refer to a clock name in the design. Output delays can be specified relative to the rising edge (default) or falling edge (-clock_fall) of the clock. Output delays can be specified relative to a pin or a port (-reference_pin) in the clock network. Clock arrival times to the reference pin or port are added to the data required time. If no -reference_pin is specified, if the output delay is specified relative to a generated clock with a single target, the clock arrival times to the generated clock are added to the data required time. If the generated clock has multiple targets, the worst case arrival time to those targets will be used. Output delays can include clock source latency. By default the clock source latency of the related clock is added to the output delay value, but when the -source_latency_included option is specified, the clock source latency is not added because it was factored into the output delay value. The maximum output delay (-max) is used for clock setup checks or recovery checks and the minimum output delay (-min) is used for clock hold checks or removal checks. If only one of -min and -max (or neither) is specified for a given port, the same value is used for both. Separate rising (-rise) and falling (-fall) required times at the port can be specified. If only one of -rise and -fall are specified for a given port, the same value is used for both. By default, set_output_delay removes any other output delays to the port except for those with the same -clock, -clock_fall, and -reference_pin combination. Multiple output delays relative to different clocks, clock edges, or reference pins can be specified using the -add_delay option. Future output delays relative to different clocks, clock edges, or reference pins that do not specify the -add_delay option will still remove previous output delays that specified the -add_delay option. The value of the targets is either a collection or a Tcl list of wildcards used to create a collection of the appropriate type. The values used must follow standard Tcl or Timing Analyzer-extension substitution rules. See help for the use_timing_analyzer_style_escaping command for details.
Example Usage	# Simple output delay with the same value for min/max and rise/fall: # 1) set on ports with names of the form myout* set_output_delay -clock clk 0.5 [get_ports myout] # 2) set on all output ports set_output_delay -clock clk 0.5 [all_outputs] # Output delay with respect to the falling edge of clock set_output_delay -clock clk -clock_fall 0.5 [get_ports myout] # Output delays for different min/max and rise/fall combinations set_output_delay -clock clk -max -rise 0.5 [get_ports myout] set_output_delay -clock clk -max -fall 0.4 [get_ports myout] set_output_delay -clock clk -min -rise 0.4 [get_ports myout] set_output_delay -clock clk -min -fall 0.3 [get_ports myout] # Adding multiple output delays with respect to more than one clock set_output_delay -clock clkA -min 0.2 [get_ports myout] set_output_delay -clock clkA -max 0.8 [get_ports myout] set_output_delay -clock clkA -clock_fall 0.6 [get_ports myout] -add_delay set_output_delay -clock clkB -min 1.1 [get_ports myout] -add_delay set_output_delay -clock clkB -max 1.5 [get_ports myout] -add_delay # This is a common mistake where output delays are accidentally removed set_output_delay -clock clkA -min 0.2 [get_ports myout] set_output_delay -clock clkB -min 1.1 [get_ports myout] -add_delay # The following removes the clkB entry. You need to always use -add_delay # when more than one clock, clock_fall or reference_pin exists set_output_delay -clock clkA -max 0.8 [get_ports myout] # The following removes the clkA entry. You need to always use -add_delay # when more than one clock, clock_fall or reference_pin exists set_output_delay -clock clkB -max 1.5 [get_ports myout] # Specifying an output delay relative to an external clock output port set_output_delay -clock clk -reference_pin [get_ports clkout] 0.8 [get_ports myout] # Specifying an output delay relative to the clock pin of a register set_output_delay -clock clk -reference_pin [get_pins regA\|clk] 0.8 [get_ports myout*]
Return Value	Code Name	Code	String Return
	TCL_OK	0	INFO: Operation successful
	TCL_ERROR	1	ERROR: Incorrect collection type. Expected a collection of type <string>.
	TCL_ERROR	1	ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist.