ID:16102 Analysis and Synthesis (quartus_map) with top-level entity name <Top-level entity name> was not run before EDA Netlist Writer. Generated IBIS model file contains models for reserved and dedicated pins only.

CAUSE: You used the Compiler to generate an IBIS Output File (.ibs) for performing board-level signal integrity verification of Intel FPGA devices with other EDA tools. Without running Analysis & Synthesis, the Quartus Prime software cannot generate the IBIS model for all user pins.

ACTION: No action is required.