ID:13808 VHDL Signal Assignment Statement warning at <location>: ignored all but the first waveform in Signal Assignment Statement

CAUSE: In a Signal Assignment Statement at the specified location in a VHDL Design File (.vhd), you used more than one waveform. However, a Signal Assignment Statement can contain only one waveform. As a result, Quartus Prime Integrated Synthesis ignored all but the first waveform in the Signal Assignment Statement.

ACTION: If you do not want Quartus Prime Integrated Synthesis to use only the first waveform for the Signal Assignment Statement, or to avoid receiving this message in the future, change the Signal Assignment Statement to a construct that can contain more than one waveform. Otherwise, no action is required.