ID:13504 Verilog HDL Event Control warning at <location>: event expression contains "|" or "||"

CAUSE: In a Verilog Design File (.v), you used "|" (bitwise inclusive or reductive OR) or "||" (logical OR) in an event expression. However, Verilog HDL uses "or" and "," for the logical OR of two event expressions. Thus, you may have intended to use one of these operators instead of "|" or "||". You should use the correct logical OR operator to avoid any potential mismatch between the simulated behavior of the design and the synthesized netlist. For example, the following Verilog HDL code mistakenly uses the expression (a | b) instead of (a or b):

always@(a | b) begin
	o = a & b;
end

            

During simulation, the Always Construct executes whenever the whole expression (a | b) changes value. If b = 1'b1, for example, then no change in the value of a will trigger the execution of the Always Construct and o retains its value. Quartus Prime Integrated Synthesis ignores this pseudo-latch behavior and implements purely combinational logic for this Always Construct.