ID:13937 VHDL Process Statement warning at <location>: inferring latch(es) for signal or variable "<name>", which holds its previous value in one or more paths through the process

CAUSE: In a process statement at the specified location in a VHDL Design File (.vhd), you updated the value of the specified object with one or more assignments. However, you did not assign a new value to the object in all possible paths through the sequence of statements in the process. Consequently, the object holds its previous value under certain conditions. For example, in the following code, the if statement assigns a new value to signal q_latch when sel = '1', but it does not assign a new value to q_latch when sel = '0'. Therefore, when sel = '0', q_latch holds its previous value.Note: Explicitly assigning q_latch to itself in the else branch of the if statement has the same effect as omitting the else branch altogether. In both cases, q_latch holds its previous value when sel = '0'.

PROCESS (a, sel)
BEGIN
	IF (sel = '1') THEN
          q_latch <= a;
    END IF;
END PROCESS;

            

When a signal or variable asynchronously holds its previous value under certain conditions, the signal or variable will infer a latch. Important: The inferred latch may or may not function correctly in your target device depending on the complexity of the conditions under which the variable holds its previous value. Integrated Synthesis will identify functional problems and issue warnings for any unsafe latches. An unsafe latch has a race condition caused by two more inputs being fed by the same signal. The synthesized behavior of a design with unsafe latches will not likely match its simulated behavior. In some cases, you may receive this warning unexpectedly. These unexpected, and sometimes false, warnings occur because Quartus Prime Integrated Synthesis does not eliminate false paths prior to checking for potential combinational loops. False paths are sequences of statements that cannot occur. For example, in the following code, the if statements update foo when sel = '1' and when sel = '0'. Quartus Prime Integrated Synthesis warns about foo because the structure of the if statements implies the possibility of a path were foo holds its previous value, that is, when sel != '1' and when sel != '0'. Though this condition may occur during simulation, it cannot occur in the synthesized netlist because sel always has a binary value. Therefore, foo does not hold its previous value under any condition. Nevertheless, Quartus Prime Integrated Synthesis will initially infer a latch for foo. In most cases, Integrated Synthesis will eliminate the latch during a later optimization step.

PROCESS (a, b, sel)
BEGIN
     IF (sel = '1') THEN
          foo <= a;
     END IF;
     IF (sel = '0') THEN
          foo <= b;
   END IF;
END PROCESS;