ID:13579 SystemVerilog warning at <location>: unique or priority keyword makes case statement complete

CAUSE: In a case statement at the specified location in a SystemVerilog Design File (.sv), you used the unique or priority keyword. In addition, the Quartus Prime software has determined that the case statement is either incomplete or potentially incomplete. If your case statement contains case items with non-constant or don't-care conditions, then the Quartus Prime software may be unable to determine completeness exactly, making the case statement potentially incomplete. The unique or priority keyword implies a complete case statement in SystemVerilog. As a result, Quartus Prime will implement selection logic as if your case statement were complete. The simulated behavior of your design may differ from its synthesized behavior if the case expression ever returns a value not covered by an explicit case item.

ACTION: If you did not intend to specify an incomplete case statement, modify the case items to make it complete or add a default case item. If you want to match simulation exactly, then remove the unique or priority keyword. Otherwise, no action is required.