ID:13289 Verilog HDL or VHDL warning at the <location>: index expression is not wide enough to address all of the elements in the array

CAUSE: In an expression at the specified location in a Verilog Design File (.v) or VHDL Design File, you indexed an array with an expression that does not have enough bits to address all of the elements in an array. For example, the following Verilog HDL fragment declares an array foo with 16/ elements, which require a 3-bit index to fully address. However, the fragment uses the 2-bit variable posto index the array.

wire [15:0] foo;
reg [1:0] pos;

               
assign o = foo[pos];

            

When analyzing an index expression, Integrated Synthesis only checks the size of the expression against the size required to index all the elements in the array; it does not attempt to compute the dynamic range of the expression. Thus, even if you do not receive this warning, your expression might not fully index the elements in the array.