ID:13032 The following tri-state nodes are fed by constants

CAUSE: The design has one or more nodes or pins that should be fed by tri-stated logic, but are fed by the constants VCC or GND instead. For example, the following Verilog design gives this warning for the bidirectional pins bidir1 and bidir2.

		module test1 (inout bidir1, bidir2); 
		assign vcc = 1'b1; 
		assign gnd = 1'b0; 
		assign bidir1 = vcc; 
		assign bidir2 = gnd; 
		endmodule 
	
               

See the sub-messages below to view a list of the affected nodes.