ID:176257 Can't pack node <name> and I/O node <name> -- clock enable signal violation

CAUSE: You turned on the Auto Packed Registers logic option, and turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However the Fitter cannot pack the nodes because the I/O cell already contains a register that clock enable signal. If two nodes have one clock enable signal, it is possible that there are other registers in the design that also had one of the above logic options turned on. If these registers were packed with the I/O cell in an earlier phase of register packing, there might be conflicting clock signals because Analysis & Synthesis generally does not pack registers into I/O cells.

ACTION: If you don't want the Fitter to pack the nodes, no action is required. Otherwise, make sure that the specified nodes have the same clock enable signal.