ID:176270 Can't pack node "<name>" and I/O cell <name> -- packing the node into the I/O cell may cause incorrect processing

CAUSE: You turned on the Auto Packed Registers logic option, and turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However, the Quartus Prime software cannot pack the nodes because doing so would violate one or more design rules intended to preserve design functionality, correct timing analysis, or design partitioning. See the submessages for details.

ACTION: If the node should be packed, then in many cases you can override the design rules by assigning the Always Allow value for the Netlist Optimizations logic option to the LCELL node. Note that design partitioning constraints may not be overridden. Also, the Quartus Prime software will not duplicate or modify the logic function of a node that generates a clock signal, regardless of the Netlist Optimizations logic option setting assigned to the node. If the node should not be packed, turn off the Fast Input Register, Fast Output Register, or Fast Output Enable Register option on the node or I/O cell or remove the PLL source synchronous mode assignment on the I/O cell.