ID:176254 Can't pack node <name> and I/O node <name> -- asynchronous clear signal violation

CAUSE: You turned on the Auto Packed Registers logic option, and turned on the Fast Input Register , Fast Output Register , and/or Fast Output Enable Register logic options for the specified nodes. The specified node can also be a PLL compensated pin in source synchronous mode. However the Fitter cannot pack the nodes because the I/O cell already contains a register that has a different asynchronous clear signal than the register to be packed. Each I/O cell can have only one distinct asynchronous clear signal. The I/O cell does not have an aload port, so any existing aload ports on the logic cell must be converted to an aclear on the I/O pin. If the design files show that two nodes have one aclear signal, there might be other registers in the design that also have one of the above logic options turned on. If these registers were packed with the I/O cell in an earlier phase of register packing, there may be conflicting aclear signals because Analysis & Synthesis generally does not pack registers into I/O cells.

ACTION: If you don't want the Fitter to pack the nodes, no action is required. Otherwise, make sure that the specified nodes have the same asynchronous clear signal.