ID:176164 Can't merge fast PLL <name> with fast PLL <name> -- merged fast PLL will use more than two clock signal feeding LVDS clock

CAUSE: The Fitter tried to merge the specified fast PLLs. However, the fast PLLs drive dedicated SERDES transmitters or receivers with more than two different clock signals. All dedicated SERDES transmitters or receivers driven by a fast PLL can have at most two differing clock signals. As a result, the Fitter could not merge the fast PLLs.

ACTION: Modify the design so that only two different clock signals of the dedicated SERDES transmitters or receivers are driven by the fast PLLs.