ID:176441 The I/O pin <name> cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).

CAUSE: The specified pin is unable to meet the timing constraints because it is a PLL compensated pin and the PLL is in source synchronous mode or ZDB mode. However, it is in conflict with the setup/hold requirements on the I/O. The given I/O timing constraints will not be met.

ACTION: Check your design and make sure that your setup/hold requirements are compatible with the PLL configuration.