ID:15084 Output clock port <name> of PLL "<name>" uses time delay

CAUSE: The specified output clock port of the specified PLL uses time delay, but the PLL does not use reconfiguration. Intel recommends using the phase shift feature of the PLL to ensure better performance.

ACTION: If you do not need to use dynamic reconfiguration of the time delay feature of the PLL, change the PLL to use the phase shift feature instead of the time delay feature.