ID:276015 Auto RAM Replacement option turned off for RAM logic "<name>"

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the Auto RAM Replacement logic option is turned off.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, turn on the Auto RAM Replacement logic option.