ID:181056 PLL counters that drive the PHY clock tree can be constrained using the set_location_assignment <PLL counter location> -to <PLL output signal> assignment.

CAUSE: PHY clock tree is driven by one or more hi-skew PLL outputs.

ACTION: Use the set_location_assignment <PLL counter location> -to <PLL output signal> assignment to constrain the phase-locked loop (PLL) counters that drive the PHY clock tree.