ID:24134 RAM logic "<name>" is uninferred due to asynchronous write logic

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the write logic for the RAM is not fully synchronous.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, ensure that the write enable, write address, and data input of the RAM are registered.