ID:11117 PLL counters that drive the PHY clock tree can be constrained using the set_location_assignment <PLL counter location> -to <PLL output signal> assignment

CAUSE: PHY clock tree is driven by one or more high skew phase-locked loop (PLL) outputs.

ACTION: Use the set_location_assignment <PLL counter location> -to <PLL output signal> assignment to constrain the PLL counters that drive the PHY clock tree.