ID:11115 PHY clock tree is driven by PLL output <output_port> (counter: <pll_counter_index>, location: <location>)

CAUSE: PHY clock tree is driven by one or more high skew phase-locked loop (PLL) outputs.

ACTION: Use the set_location_assignment <PLL counter location> -to <PLL output signal> assignment to constrain the PLL counters that drive the PHY clock tree.