ID:13840 VHDL Loop Statement error at <location>: loop must terminate within <number> iterations

CAUSE: In a loop statement at the specified location in a VHDL Design File (.vhd), you specified a loop that does not terminate within 10,000 iterations. This message may occur because the loop's terminating condition depends on a signal or non-constant variable. You may also have forgotten to increment a variable in the loop's terminating condition. To avoid an infinite loop or memory exhaustion, Quartus Prime Integrated Synthesis prematurely terminated the synthesis of your design.

ACTION: Check the loop for errors or non-constant terminating conditions. If you can guarantee that your loop will exit within 10,000 iterations, you can bypass this error by adding an explicit exit statement that terminates the loop after N < 10,000 iterations. If your loop should iterate more than 10,000 times, you will need to factor the loop into multiple loops with 10,000 or fewer iterations each.