ID:13685 VHDL error at <location>: subtype indication cannot contain <>

CAUSE: In a VHDL Design File (.vhd) at the specified location, you used the undefined range symbol (<>) in a subtype indication. However, the subtype indication must have a defined range for the subtype. For example, you may have already constrained the subtype.

ACTION: Change the undefined range symbol in the subtype indication to a defined range.