ID:13932 VHDL error at <location>: can't implement clock enable condition specified using binary operator "<name>"

CAUSE: In an expression at the specified location in a VHDL Design File (.vhd), you attempted to specify an enable condition for a clock edge. However, Quartus Prime Integrated Synthesis cannot infer a register to implement the clock enable condition because you attempted to specify the clock enable condition using the specified binary operator, which is not AND. You must combine a clock edge and an enable signal only with a binary AND.

ACTION: Change the expression so it uses a binary AND operator to specify an enable condition for a clock edge. For example, in the following code, the expression rising_edge (clk) AND enable correctly specifies a clock enable condition:

PROCESS (clk)
BEGIN
    IF(rising_edge(clk) AND enable) THEN
        q <= data;
    END IF;
END PROCESS;