ID:13607 VHDL Subprogram Specification error at <location>: subprogram "<name>" is a homograph of another object in the same declarative region

CAUSE: In a VHDL design file (.vhd) at the specified location, you declared the specified subprogram. However, the subprogram conflicts with another declaration in the same scope. The other declaration can be an object that does not support overloading, or the other declaration can be an subprogram with the same name and signature (return type + argument types).

ACTION: If the subprogram conflicts with another object that does not support overloading, then assign unique names to both objects. Otherwise, modify the subprogram signatures so that they are not homographs.