ID:13931 VHDL Binding Indication error at <location>: can't bind component port "<name>" with mode "<text>" to design entity port "<name>" with incompatible mode "<text>"

CAUSE: In a Binding Indication at the specified location in a VHDL Design File (.vhd), you associated a component with a design entity. Because you did not use Port Map Aspects in the Binding Indication to explicitly associate component ports with design entity ports, Quartus Prime Integrated Synthesis attempted to bind the specified component port to the design entity port with the same name. However, Quartus Prime Integrated Synthesis cannot bind the ports because the component port has the specified mode, which is compatible with the specified mode for the design entity. For example, the component port may have mode IN, which is incompatible with a design entity port that has mode OUT.

ACTION: Declare the component and design entity ports so the ports have compatible modes. If Quartus Prime Integrated Synthesis must not bind component and design entity ports based on name, use Port Map Aspects in the Binding Indication to explicitly associate ports for each instantiation of the component.