ID:13370 Verilog HDL Module Instantiation error at <location>: arrays of Module Instantiations are not supported

CAUSE: In a Verilog Design File (.v) at the specified location, you instantiated an array of Module Instantiations. Although arrays of Module Instantiations are supported in Verilog HDL, they are not supported in the Quartus Prime software.

ACTION: Rewrite the Verilog Design File to implement an array of modules using a Generate Statement instead of an array of Module Instantiations. For example, the following sample design instantiates eight two-input AND gates using an array of Module Instantiations:

module my_and(in_a, in_b, out);
   input in_a, in_b;
   output out;
   assign out = in_a & in_b;
endmodule
module my_and_array (in1, in2, out);
   input [7:0] in1, in2;
   output [7:0] out;
   my_and and_array[7:0] (in1, in2, out);
endmodule

If this design is rewritten with a Generate Statement, as shown in following sample design, the design will then compile successfully.

module my_and(in_a, in_b, out);
    input in_a, in_b;
    output out;
    assign out = in_a & in_b;
endmodule
module my_and_array (in1, in2,out);
   input [7:0] in1, in2;
   output [7:0] out;
   genvar i;
   generate for (i = 0; i<8; i=i+1) begin:my_label_for_each_bit
         my_and and_array(in1[i], in2[i], out[i]);
   end
   endgenerate
endmodule