ID:13454 Verilog HDL syntax error at <location>: comment block must have beginning comment delimiter (slash and asterisk)

CAUSE: In a block comment in a Verilog Design File (.v) at the specified location, you used an ending comment delimiter (asterisk and slash, or */) without a corresponding beginning comment delimiter (slash and asterisk, or /*). You must use a /* prior to every */ in the Verilog Design File.

ACTION: Add a /* at the beginning of the comment block that ends with the unmatched */