ID:13392 Verilog HDL error at <location>: replication multiplier is not constant

CAUSE: In a Verilog Design File (.v) at the specified location, you used a replication operation with a multiplier value that is not constant, for example, assign out = {myvar{in}} where myvar is a reg or integer. The multiplier value in a replication operation must be a constant so that the width of the expression can be computed during synthesis.

ACTION: Edit the design to make sure all replication statements have constant multipliers. For example, in the following excerpt of a sample design, the i variable in the replication operation would be reported as an error, even though the design specifies that the value of i will always be 4. To correct this error, you should replace the variable i in the replication operation with the constant value 4.

reg [1:0] in;
integer i = 4;

               
assign out = {i{in};