ID:13533 Verilog HDL Port Connection error at <location>: output or inout port "<name>" must be connected to a structural net expression

CAUSE: At the specified location in a Verilog Design File (.v), you connected the specified output or inout port to an invalid expression. Verilog HDL requires that you connect output and inout ports to structural net expressions, which are expressions consisting of:

• a scalar net
• a vector net
• a constant bit-select of a vector net
• a part-select of a vector net
• a concatenation of structural net expressions

For example, you cannot connect an output or inout port to a constant or to a variable, e.g. a reg.