ID:13301 Verilog HDL error at <location>: values cannot be assigned directly to all or part of array "<name>" - assignments must be made to individual elements only

CAUSE: In a Verilog Design File (.v) at the specified location, you assigned values directly to the entire specified array or to a part of the specified array. However, Verilog requires that assignments be made to individual elements only.

ACTION: Assign values to individual array elements, as shown in the following example:

module mem_fixed(a, x);
   input [1:0] a;
   output x;
   reg mem1bit[1:0];
   always begin
      mem1bit[1] = a[1];
      mem1bit[0] = a[0];
   end
endmodule