ID:13332 Verilog HDL error at <location>: hierarchical name "<name>" cannot reference signal in another hierarchy

CAUSE: In a Verilog Design File (.v) at the specified location, you used a hierarchical name to reference a signal in another hierarchy. The Quartus Prime software does not allow you to reference an internal signal of another module.

ACTION: Change the design to reference only signals that are declared within the current module, or its inputs.