ID:13595 SystemVerilog error at <location>: can't pass values between formal ref "<name>" and actual with non-equivalent types

CAUSE: In a function call or task enable at the specified location SystemVerilog Design File (.sv), you passed an expression to the specified argument, which was declared with the ref keyword. However, the expression type is not equivalent to the argument's declared type. SystemVerilog requires an equivalent type in this scenario.

ACTION: Modify the type of the expression or the type of the referenced argument to make them equivalent.