ID:142031 Partition "<name>" contains a signal or variable declared in the VHDL or System Verilog packages. Bottom-up incremental compilation flow for the signal or variable declared in the VHDL or System Verilog packages is not supported in this version of the Quartus Prime software
CAUSE: The specified partition contains a signal or variable declared in the VHDL or System Verilog packages. However, bottom-up incremental compilation flow for the signal or variable declared in the VHDL or System Verilog packages is not supported in this version of the Quartus Prime software.
ACTION: No action is required.