ID:13074 The open-drain buffer "<name>" directly or indirectly feeds itself.

CAUSE: The specified open-drain buffer directly or indirectly feeds itself. Such a loop is not legal. This can happen when the open-drain buffer has fan-in and fan-out to the same bidirectional pin. For example, the following Verilog design gives this error:

		module test1 (bidir); 
		inout bidir; 
		wire tri_wire; 
		assign tri_wire = bidir; 
		assign bidir = tri_wire ? 1'b0 : 1'bZ; 
		endmodule