ID:18612 READDATAVALID signal for secondary memory controller's Avalon Memory Mapped bus is not connected for memory interface IP "<IP instance name>". Connect this port to an FPGA core signal.

CAUSE: Fitter expects certain ports in the memory interface IP to be driven by a core signal. One of such ports is not connected in the current design.

ACTION: Update the design to connect the memory interface port listed in the error message.