ID:19868 Design contains too many EMIF/PHYLite systems with unique logic connected to the debug interface port

CAUSE: Each EMIF/PHYLite system with the debug interface port exposed and connected to unique logic must be placed in its own I/O column. When the number of such EMIF/PHYLite systems exceeds the total number of I/O columns in the device, this error occurs.

ACTION: Only one EMIF/PHYLite debug interface should be instantiated per I/O column. If multiple EMIF/PHYLite IP cores exists per I/O column that must share the debug interface and logic, these IP cores must be daisy-chained together. Consult the EMIF/PHYLite documentation for details. If you no longer need to use the EMIF/PHYLite debug interface, you can resolve the error by regenerating the EMIF/PHYLite IP core with the debug interface disabled, and recompiling the design.