ID:18790 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different write clock source. Port Clear is configured as sclear input must be connected to a Hyperflex register with same write clock source.
CAUSE: Port Clear configured as sclear input must be connected to a Hyperflex register with same write clock source.
ACTION: Modify the design to connect clr to a Hyperflex register with same write clock source.