ID:18793 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different read and write clock sources. Port Clock Enable 1 input when connected to a Hyperflex register must be connected with same clock source.

CAUSE: Port Clock Enable 1 input must be connected to a Hyperflex register with same read and write clock source.

ACTION: Modify the design to connect ena1 with a Hyperflex register to have same read and write clock source.