ID:18791 WYSIWYG primitive "<lutram name>" and WYSIWYG primitive "<reg name>" are connected to different write clock source. Port Clock Enable 1 input must be connected to a Hyperflex register with same write clock source.

CAUSE: Port Clock Enable 1 input must be connected to a Hyperflex register with same write clock source.

ACTION: Modify the design to connect ena1 to a Hyperflex register with same write clock source.