ID:19206 DSP block WYSIWYG primitive "<atom name>" has one or more registers using clock "<bit index>" but port CLK[<bit index>] is either not connected or driven by VCC or GND.

CAUSE: The DSP block WYSIWYG primitive has one or more registers using the specified clock settings but the specified CLK port driving the registers are either not connected or is driven by VCC or GND.

ACTION: Make sure the register clock settings are correct and connect the specified port to a valid signal.