ID:15669 inclk port of Clock Control Block "<name>" must be driven by <number> PLLs but is driven by <number> PLLs

CAUSE: The specified inclk port of the Clock Control Block is driven by the specified number of PLLs that is more than the total number of PLLs that must drive the inclk port. The Clock Control Block can only be driven by the specified number of PLLs.

ACTION: Modify the design and reduce the number of PLLs that drive the Clock Control Block to the specified number.