ID:22849 Intel FPGA IP instantiated in the design requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ, or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file.

CAUSE: The requirements on the initialization clock for the Intel FPGA IP instantiated in the design have not been met.

ACTION: Set DEVICE_INITIALIZATION_CLOCK to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ, or OSC_CLK_1_125MHZ. To choose the initialization clock source, in the Intel Quartus Prime software, click 'Device and Pin Options > General > Device initialization clock source' or directly set it in the QSF as 'set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_25MHZ'. Remember that changing the DEVICE_INITIALIZATION_CLOCK option may require additional pin planning.