Metastability Analysis

Specifies how the Timing Analyzer identifies registers as being part of a synchronization register chain for metastability analysis.

A synchronization register chain is a sequence of registers with the same clock with no fan-out in between, which is driven by a pin or logic from another clock domain.

Table 1. Synchronizer Identification Options
Option name Meaning
Off Timing Analyzer does not identify the specified registers, or the registers within the specified entity, as synchronization registers.
Auto Timing Analyzer identifies valid synchronization registers that are part of a chain with more than one register that contains no combinational logic
Forced if Asynchronous Timing Analyzer identifies synchronization register chains if the software detects an asynchronous signal transfer, even if there is combinational logic or only one register in the chain.

Registers that are identified as synchronizers are optimized for improved Mean Time Between Failure (MTBF) as long as the Optimize Design for Metastability option is enabled.

If a synchronization register chain is identified with the Forced if Asynchronous option, then the Timing Analyzer reports the metastability MTBF for the chain. MTBF is not reported for automatically-detected register chains; you can use the Auto setting to generate a report of possible synchronization chains in your design. If a synchronization register chain is identified with the Forced if Asynchronous option, then the Timing Analyzer reports the metastability MTBF for the chain when it meets the design timing requirements.

Scripting Information

Keyword: synchronizer_identification

Settings: forced_if_asynchronous | auto* | off

*default