Simulation Flows

The Quartus® Prime software supports various simulation flows.
Table 1. Simulation Flows
Simulation Flow Description
Scripted Simulation Flows Scripted simulation supports custom control of all aspects of simulation, such as custom compilation commands, or multipass simulation flows. Use a version-independent top-level simulation script that sources Quartus® Prime-generated IP simulation setup scripts. The Quartus® Prime software can generate a combined simulator setup script for all IP cores, for each supported simulator.
Run Simulation You can use the Run Simulation feature in the Quartus® Prime Pro Edition software to integrate your supported third-party EDA simulator and automate generation of simulator-specific files and setup scripts, compilation of simulation libraries, and launch of your simulation.
Qrun Flow The Quartus® Prime Pro Edition software now supports a new Qrun flow for IP generation in Platform Designer. The Qrun flow optionally creates simulation files, including the functional simulation model, and any testbench (or example design).The Qrun flow, for use with only the QuestaSim* and Questa* Intel FPGA Edition simulators, is an enhancement over the traditional flow that automatically combines the compile, optimize, and simulate functions into a single step.
NativeLink Simulation Flow NativeLink automates Quartus® Prime integration with your EDA simulator. Setup NativeLink to generate simulation scripts, compile simulation libraries, and automatically launch your simulator following design compilation. Specify your own compilation, elaboration, and simulation scripts for testbench and simulation model files. Do not use NativeLink if you require direct control over every aspect of simulation.
Specialized Simulation Flows Specialized simulation flows support various design scenarios:
  • For simulation of example designs, refer to the example design pr IP documentation.
  • For simulation of Platform Designer designs, refer to Simulating Platform Designer Systems in Quartus® Prime Standard Edition User Guide: Platform Designer.
  • For simulation of the Nios® V processor, refer to the Nios V Embedded Processor Design Handbook.